With the constant drive towards increasing both the operating speeds and capacity of DRAM devices, advances in DRAM technology are directed at reductions in device minimum feature size (F) and achieving more compact cell layouts through reduced device footprint. Reduction in scale of planar DRAM devices is limited by stringent leakage requirements, however. A reduction in gate poly length requires thinner gate oxides, while the reduction in gate poly length (i.e., channel length) requires increased channel doping to avoid short channel effects. High doping levels, on the other hand, increase junction leakage which, in turn, decreases data retention time. These and other challenges surrounding the scaling of planar DRAM devices have provided the motivation for vertical transistors. These devices introduce both additional degrees of freedom as well as constraints in the design of conventional planar devices.
The design of the resulting vertical devices has involved an asymmetric cell structure, in which the transistor and the corresponding buried strap (e.g., one-sided strap or “OSS”) are formed along the upper region of a trench capacitor. The OSS lies along one vertical edge of the cell device between the transistor and capacitor. However, positioning multiple devices in close physical proximity to one another introduces a potential for electrical cross-talk between cells, entailing defective operation of the devices. This risk has been mitigated by introducing shallow trench isolation (“STI”), which provides lateral isolation between adjacent cells. The STI may extend approximately 200–400 nm below the buried strap.
This resulting configuration, while theoretically advantageous, suffers from manufacturing difficulties that are related to the fabricated STI. As the feature size of the vertical DRAM device decreases, the resulting aspect ratio of the device, defined as depth of trench divided by trench separation, increases. This makes the device difficult to form using known processes without the formation of unacceptable voids and other defects. In essence, the resulting increase in aspect ratio of a trench, which can fall in the range of 4–8, may turn out to be difficult to fill properly with oxide. Though intended to neatly fill it from the bottom, as the oxide is deposited into the space allocated for the formation of the STI it tends also to grow at the side walls. This growth can occur to such an extent that the resulting side wall formations actually touch, forming a structure having a shape reminiscent of that of a bishop's mitre. This undesired structure interrupts the downward flow of oxide, leading to the formation of undesirable voids. In addition to being unpredictable, the voids undermine the electrical characteristics of the STI and defeat its purpose.
Accordingly, there is a need for a solution to the problems associated with forming STI as the device minimum feature size (F) shrinks. Moreover, there is a need to form STI using a practical approach to the manufacture of vertical DRAMs.